An FPGA Implementation of the Linear Cryptanalysis

This paper deals with cryptographic concepts. It presents a hardware FPGA implementation of linear cryptanalysis of DES. Linear cryptanalysis is the best attack known able to break DES faster than exhaustive search. Matsui’s original attack [4, 5] could not be applied as such, and we had to implement a modified attack [1] to face hardware constraints. The resulting attack is less efficient than Matsui’s attack, but fits in our hardware and breaks a DES key in 12-15 hours on one single FPGA, therefore becoming the first practical implementation to our knowledge. As a comparison, the fastest implementation known so far used the idle time of 18 Intel Pentium III MMX, and broke a DES key in 4.32 days. Our fast implementation made it possible for us to perform practical tests, allowing a comparison with theoretical estimations.